SOC Timing Engineer

Job Overview

STA Design Engineer

Responsibilities

• Responsible for timing closure and sign‑off of FPGA/SoC and subsystem timing.
• Perform static timing analysis, derive interface timing constraints for partitions, and conduct final timing sign‑off.
• Collaborate closely with design and architecture teams on timing convergence analysis.
• Work with the physical design team to achieve timing closure.

Qualifications

• Experience in static timing analysis and industry‑standard EDA tools such as Primetime/PTPX.
• Strong understanding of timing constraints, clocking, and PVT modeling.
• Tape‑out experience, including work on technology nodes of 10nm or lower.
• BE/MS/PhD in Electronics/Electrical Engineering with 3+ years of experience in physical design and timing closure/sign‑off.
• Excellent communication, problem‑solving, and analytical skills.

Job Details