Senior Verification Engineer – RISC-V Cores

TechBiz Global GmbH is seeking a Senior Verification Engineer to join a team developing RISC-V CPU cores in Helsinki. The ideal candidate will have over 8 years of industrial experience and expertise in SystemVerilog and UVM.

This position involves ensuring correctness in complex digital designs using advanced verification methodologies. Strong problem-solving and teamwork abilities are essential for success in this role.