Senior Physical Design Engineer - FinFET SerDes & P&R

UST in Penang, Malaysia, seeks a skilled physical design engineer to lead analog/mixed-signal layout for high-speed interfaces in deep submicron FinFET technologies. You will handle synthesis, P&R, timing closure, PI/SI analysis, and DFM/DFR verification with Cadence, Synopsys, and Mentor tools.

Key responsibilities include floor planning, power grid design, ECO generation, UPF flows, and LEF/DEF creation. Collaboration in a dynamic team is essential to deliver reliable data and meet EMIR