Job Description
We are seeking a Senior Physical Design and Timing Engineer to work on high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block, cluster, and full‑chip levels.
What you’ll be doing:
- Drive physical design and timing of high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.
- Help in driving frontend and backend implementation from RTL to GDSII, including synthesis, equivalence checking, floor‑planning, timing constraints, timing and power convergence, and ECO implementation.
- Work in a cross‑functional environment interacting with multiple teams.
- Apply knowledge and experience to improve the convergence flows working with the Methodology Team.
What we need to see:
- BS (or equivalent) in Electrical or Computer Engineering with 5+ years of experience or MS with 3+ years of experience in s...