Senior IP Designer Engineer

Job Description

We are seeking a Senior IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.

Responsibilities

Build and maintain Connectivity IP portfolios for Lattice FPGA, translating specifications into high-speed RTL design with emphasis on Performance, Power and logic utilization, in collaboration with architects. Provide technical leadership and guidance to the team.

Requirements

Key Skills

• Experience in high speed SERDES and video protocols (e.g. HDMI, SDI, DisplayPort, MIPI) is a plus
• Hands‑on experience in FPGA RTL design, logic verification, debug and timing closure is preferred
• Programming skills (e.g.: C/C++, Perl, TCL or Python)...