Senior Front-End ASIC Engineer - RISC-V IP Integration

Bitdeer is seeking an experienced engineer to lead RISC-V core integration with external accelerators in a high‑performance ASIC environment. You will tailor CPU features and architecture, focusing on power, performance, and area constraints.

The role requires strong RTL design experience (Verilog/SystemVerilog) and collaboration with cross‑functional teams to optimize IP integration across pre/post‑silicon stages.