Job Description
Senior CPU RTL Design Engineer
_corporate_fare_ Google _place_ Mountain View, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
+ 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
+ Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).
**Preferred qualifications:**
+ PhD in Electrical Engineering or Computer Science, or a related field.
+ Experience leading front-end design for modern processor components or AI accelerators.
+ Experience with ARM Instruction Set Architecture or CPU subsystems.
+ Experience with SoC ...
_corporate_fare_ Google _place_ Mountain View, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
+ 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
+ Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).
**Preferred qualifications:**
+ PhD in Electrical Engineering or Computer Science, or a related field.
+ Experience leading front-end design for modern processor components or AI accelerators.
+ Experience with ARM Instruction Set Architecture or CPU subsystems.
+ Experience with SoC ...