Senior CPU Front-End & RISC-V Core Engineer

Bitdeer is seeking a senior CPU IP integration engineer to drive RISC-V core integration with external accelerators, tailoring features to meet strict PPA targets and performing RTL modifications. You will work with performance, middle-end, and back-end teams to ensure successful IP integration and robust verification.

The role requires hands-on Verilog RTL experience, scripting skills, and a strong background in CPU architecture.