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Principal Verification Engineer

Rambus

📍 San Jose, California, United States

Full-time Engineers
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Job Description

Responsibilities

  • Technical lead for full chip and/or blocks level verification 

  • Define verification plan in coordination with Architects, Logic and Mixed-signal designers

  • Implement testbenches, monitors and scoreboards using UVM methodology 

  • Achieve code coverage goals and ensure thoroughly verified designs 

  • Work with the Lab/System team for test plan, silicon bring up and debug 

  • Work in a dynamic and interdisciplinary R&D group contributing to flow and methodology development

  • Mentor junior designers 

    • Qualifications


  • MS EE and 10+ years or PhD EE and 7+ years’ experience of Verification 

  • Significant Experience with coding in System Verilog or Verilog and UVM methodology 

  • Experience in verification of DDR memory interfaces is higly desirable 

  • Significant Experience with standard ASIC Verification flow/software tools

    • Job Details

    Location San Jose, California
    Job Type Full-time
    Category Engineers
    Posted July 21, 2026
    Deadline August 30, 2026