Principal Design Engineer
C
Cadence Design Systems, Inc.
📍 Shanghai, China, China
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
+ Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products.
+ Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.
+ Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
+ Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.
+ Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.
Job Requirements:
+ Th...
Key Responsibilities
+ Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products.
+ Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.
+ Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
+ Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.
+ Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.
Job Requirements:
+ Th...