Job Description
Job Summary
We are seeking a skilled Physical Design Engineer with approximately 4 years of hands-on experience in the full-chip or block-level physical implementation of ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flows, timing closure, and signoff activities for advanced technology nodes.
Key Responsibilities
- Perform block-level and/or full-chip physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
- Own timing closure across all implementation stages (pre-CTS, post-CTS, post-route)
- Handle congestion, IR drop, and power optimization
- Run and debug DRC, LVS, and physical verification issues
- Perform ECO implementation to address timing, power, and functional fixes
- Work closely with RTL, STA, DFT, and Signoff teams to resolve design issues
- Analyze and fix timing violations (setup, hold, DRV) across multiple modes and corners
We are seeking a skilled Physical Design Engineer with approximately 4 years of hands-on experience in the full-chip or block-level physical implementation of ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flows, timing closure, and signoff activities for advanced technology nodes.
Key Responsibilities
- Perform block-level and/or full-chip physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
- Own timing closure across all implementation stages (pre-CTS, post-CTS, post-route)
- Handle congestion, IR drop, and power optimization
- Run and debug DRC, LVS, and physical verification issues
- Perform ECO implementation to address timing, power, and functional fixes
- Work closely with RTL, STA, DFT, and Signoff teams to resolve design issues
- Analyze and fix timing violations (setup, hold, DRV) across multiple modes and corners