Penang Timing Closure Engineer, FPGA/SoC

754 Altera Semiconductor Technology (M) Sdn. Bhd. in Penang, Malaysia is seeking a STA Design Engineer to drive timing closure for FPGA/SoC and subsystems.

The role focuses on static timing analysis, deriving timing constraints, and coordinating with design and architecture teams to converge timing. The ideal candidate has strong experience with timing constraints, clocking, PVT modeling, and is proficient with Primetime/PTPX tools, plus a BE/MS/PhD in Electronics or related field and 3+ years