Memory Layout Technology Lead at Infosys
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Infosys
📍 burnaby, metro vancouver regional district, Canada
Job Description
Elevate your career as a Memory Layout Technology Lead with Infosys in Vancouver, BC. Collaborate with design engineers on cutting-edge memory architecture and layout creation.
Infosys is seeking a skilled professional in Memory Layout. This role requires at least 5 years of experience in Compiler and Custom Memory Layout design. You will integrate layout designs with circuit teams, leveraging your knowledge of FinFET technology, DRC limitations, and optimized layouts for performance enhancement.
Key Responsibilities:
• Collaborate with engineers on memory data path layout
• Design memory leafcell layout libraries from scratch
• Optimize layouts for enhanced performance
• Conduct physical verification flows and debugging
• Communicate effectively with the project team
Requirements:
• Bachelor's degree or 3 years of relevant experience
• Minimum 5 years in Compiler/Memory Layout design
• Strong understanding of memory architectures
• Proficiency in Ca...
Infosys is seeking a skilled professional in Memory Layout. This role requires at least 5 years of experience in Compiler and Custom Memory Layout design. You will integrate layout designs with circuit teams, leveraging your knowledge of FinFET technology, DRC limitations, and optimized layouts for performance enhancement.
Key Responsibilities:
• Collaborate with engineers on memory data path layout
• Design memory leafcell layout libraries from scratch
• Optimize layouts for enhanced performance
• Conduct physical verification flows and debugging
• Communicate effectively with the project team
Requirements:
• Bachelor's degree or 3 years of relevant experience
• Minimum 5 years in Compiler/Memory Layout design
• Strong understanding of memory architectures
• Proficiency in Ca...