At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities :
Design Verification for interconnect IP and Tensilica Processor subsystems.Relevant experience in interconnect and subsystems is strongly preferredCrafting verification plans and executing on those plans to verify highly complex and configurable designs.Responsible for coverage collection and closureWork closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scopeResponsible for creating / working with UVM based DV environment.Required Skills and Experience:
7+ years of design verification experienceBS (or higher) in EE/Computer EngineeringStrong technical and interpersonal skillsExcellent knowledge of Interconnects, NoCs and design verification fundamentals.Excellent knowledge and command ove...