Innovative Standard Cell Layout Engineer

Qualcomm seeks a layout engineer to design and develop physical layouts for logic standard cells using Cadence Virtuoso, with SKILL and Python for automation. You will collaborate with circuit designers to ensure layouts meet performance and reliability requirements, and perform comprehensive layout verification.

Responsibilities include DRC/LVS/ERC checks, managing layout databases, and clear communication of design status within a globally distributed team including the US, Taiwan, and India.