Infosys Memory Team Layout Engineer
I
Infosys
📍 burnaby, metro vancouver regional district, Canada
Job Description
Join Infosys as a Memory Team Layout Engineer in Vancouver, BC, focusing on innovative memory layout design and collaboration with circuit engineers. This role emphasizes performance optimization.
As part of the Memory Team, you will boast 5+ years of experience in compiler/custom memory layout design and contribute to designing new layouts. You will need proficiency in FinFET technology and hands-on experience with physical verification processes like DRC and LVS. This role supports the construction of superior memory architectures.
Key Responsibilities:
• Develop top-level memory layouts and coordinates with circuit team
• Design memory leafcell libraries from inception
• Enhance performance through optimized layout designs
• Perform physical verification, debugging, and compliance checks
• Engage in effective communication throughout projects
Requirements:
• Bachelor’s degree or 3 years relevant industry experience
• At least 5 years in specialized layo...
As part of the Memory Team, you will boast 5+ years of experience in compiler/custom memory layout design and contribute to designing new layouts. You will need proficiency in FinFET technology and hands-on experience with physical verification processes like DRC and LVS. This role supports the construction of superior memory architectures.
Key Responsibilities:
• Develop top-level memory layouts and coordinates with circuit team
• Design memory leafcell libraries from inception
• Enhance performance through optimized layout designs
• Perform physical verification, debugging, and compliance checks
• Engage in effective communication throughout projects
Requirements:
• Bachelor’s degree or 3 years relevant industry experience
• At least 5 years in specialized layo...