Job Description
Job Description:
Scan & ATPG
• Strong understanding of Siemens Tessent Tools for ATPG with SSN methodology
• Experience in ICL, PDL, Stuck-at and transition fault pattern generation
• Good understanding on scan coverage and experience in carrying out coverage analysis.
• Experience in Timing and no Timing gate level simulations and debugging simulation failures.
• Experience in carrying out DFT DRC checks in RTL and analyzing the violations.
• Strong understanding of Scan structures, IEEE1149.1, IEEE1687, ATPG methodology and flow.
• Good understanding of timing constraints, synthesis flow and scan insertion using DC/FC
• Strong TCL/scripting knowledge
MBIST • Strong understanding of Siemens Tessent tools for MBIST insertion and verification
• Experience in MBIST insertion in RTL, pattern generation.
• Experience in ICL, PDL, IEEE1149.1, IEEE1687, MBIST verific...