Design For Test Engineer (Einfochips Inc)

DFT implementation for 3nm and 5nm Networking chips, IP DFT work

RTL checks for scan-insertion compatibility using Synopsys Spyglass

Scan-Insertion using Tessent TestKompress

ATPG pattern generation:

Compressed and Uncompressed Mode

Mentor Tessent, Cadence Modus & Synopsys Tetramax

Pattern Simulation:

Without timing, With timing for different corners

VCS

Mismatch debug using

Scripting with Perl, Shell, TCL:

DAeRT - DFT flow enhancement/automation in project

Makefile enhancement using extended scripts and targets for flow enhancement

MBIST Insertion and Verification:

MBIST Insertion and Verification done on block on top

Silicon debug and bring-up done for block and top

IEEE ...