ASIC Front-End Designer - Open-Source RTL & Tapeout

CERN is seeking a talented engineer to design, simulate, and verify the digital front-end for the next-generation ASICs used in radiation monitoring and safety-critical systems. You will prepare RTL for tapeout, work with open-source EDA tools, and assist after-fabrication bring-up and validation.

Ideal candidates have experience with RTL to GDSII, floorplanning, and hardware debugging. A hybrid work model is offered with opportunities for professional growth within CERN's HSE-TS-IMS division.